Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Area of Science:

• Computer Engineering
• Cryptography
• Cybersecurity

Background:

• Cryptographic algorithms like AES are crucial for data security in connected systems, especially automotive environments.
• Hardware implementations of AES are vulnerable to differential fault analysis, compromising secure communications.
• Existing fault detection techniques for AES, such as iterative and parallel architectures, have limitations, necessitating exploration of pipelining.

Purpose of the Study:

• To propose a novel hybrid pipeline hardware architecture for the Advanced Encryption Standard (AES) algorithm.
• To focus on enhancing error and fault detection capabilities within the AES cryptographic process.
• To address the challenges of balancing high throughput, low power consumption, and reduced hardware resources in pipeline designs with fault tolerance.

Main Methods:

• Developed a hybrid pipeline architecture combining hardware and time redundancy.
• Implemented a pipeline structure for ciphering data blocks multiple times (five times).
• Integrated a voting module for error detection and a decision tree to optimize the evaluation process.

Main Results:

• The proposed architecture was analyzed and implemented on various FPGA technologies.
• Achieved a throughput of 0.479 Gbps on a Virtex-7 FPGA.
• Reported an efficiency of 0.336 Mbps/LUT on a Virtex-7 FPGA.

Conclusions:

• The novel hybrid pipeline architecture effectively enhances error and fault detection for AES.
• The design balances performance metrics like throughput and efficiency with robust security features.
• This approach offers a promising solution for securing communications in sensitive environments like connected vehicles.